1. Field of the Invention
The present invention relates generally to a one-dimensional pixel (picture element) data encoder for use in a facsimile apparatus, and more specifically to such an encoder by which coding is implemented at a considerably low internal clock rate.
2. Description of the Prior Art
Before turning to the present invention, it is deemed preferable to discuss two known facsimile apparatus with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram schematically showing a concept of a conventional facsimile apparatus having a large capacity memory by which a constant speed scanning is attained. A document reader 10 is arranged to obtain pixel data sequences on a line-by-line basis by scanning a black and white document. The line pixel data sequences 12 thus obtained are successively sent to a memory 14 which has a storage capacity corresponding to one sheet of a document. The pixel data stored in the memory 14 are sent to an encoder 16 which encodes the pixel data sequences applied thereto according to the algorithm proposed in the recommendation T4 of CCITT (The International Telegraph and Telephone Consultative Committee). The encoded pixel data outputted from the encoder 16 are stored in an encoded data memory 18. A transmitter (TX) 20 receives the encoded data from the encoded data memory 18 in synchronism with a transmission speed. Transmitter 20 modulates the data received and sends the data out over a transmission line.
The FIG. 1 arrangement enables the document reader 10 to scan a document at a constant rate even in the case of alternate occurrences of black and while pixels. This is because the pixel data memory 14 has a storage capacity sufficient to compensate for the encoding speed under a worst coding efficiency condition.
However, the apparatus shown in FIG. 1 has encountered the problem of high manufacture cost in that the full page memory 14 is essential. For example, in the case where a document sheet having a paper size of 256 mm.times.362 mm is scanned with a pixel density of 16-dot/mm.times.15.4-dot/mm, 3 Mega Bytes memory is necessary. Accordingly, large cost reductions are extremely difficult to achieve.
In order to obviate the need for the aforesaid full page memory, run length coding techniques have been proposed. The run length coding is the coding of lengths of consecutive black and white picture elements for the purpose of transmission redundancy reduction. This technique allows for the compression of two-level picture data obtained by scanning a black and white document.
One example of a pixel data encoder utilizing the run length coding for eliminating a full page memory will be briefly referred to in connection with FIG. 2. This arrangement has been disclosed in Japanese Patent Application No. 1-276870 filed Oct. 23, 1989 and provisionally published under publication No. 3-136575 on Jun. 11, 1991.
A run length calculator 22 receives one-dimensional binary data sequence 24 in synchronism with a data acquisition sync clock 28 and a line sync clock 26. The run length calculator 22 determines the lengths of consecutive black and white pixels. A FIFO (First In First Out) memory 30 receives the run length information 23 using the data acquisition clock 28. In the case where the document sheet has a size 256 mm.times.362 mm and the scanning density 8-dot/mm, the maximum run length is 2048 dots (viz., 11 bits). Since one additional bit is necessary for discriminating a color (black or white) of the consecutive pixels, the bit length of the run length information 23 totals 12 bits in this instance. The output of the FIFO memory 30 is derived using a data processing clock 29.
A run length encoder 32 is supplied with the run length information stored in the FIFO memory 30 in synchronism of the clock 29 and, encodes the run length information according to "Recommendation T4" of CCITT. In more specific terms, the encoder 32 supplies a ROM (Read Only Memory) 34 with an 8-bit code word which consists of a color discriminating bit (1-bit), a make-up/terminating discriminating bit (1-bit) and a run length (6-bit). The 8-bit code word is converted at the ROM 34 using a look-up table provided therein, into a code (13-bit) and a code length (4-bit). A P/S (Parallel Serial) converter 36, which follows the ROM 34, picks up significant bits of the code data based on the code length. Following this, the converter 36 implements parallel-to-serial conversion on the significant bits and output the significant bits therefrom. The data processing at the P/S converter is synchronized by the clock 29.
With the arrangement shown in FIG. 2, the amount of encoding of the pixel data reaches the maximum when white and black pixels occur alternately. In this case, according to the above-mentioned "Recommendation T4", the code length assigned to a white run length l is 6-bit while the code length assigned to a black run length l is 3-bit. Accordingly, the average amount of codes per pixel is 4.5-bit. This means that the speed of the data processing clock 29 has to be 4.5 times of that of the data acquisition clock 28. Thus, it is difficult to increase the clock rate of the clock 28 in that the maximum speed of the clock 29 is limited by the data processing capacity of the elements used in the encoder.